Faculty Directory
Nikos Hardavellas

Professor of Computer Science

Professor of Electrical and Computer Engineering

Contact

2233 Tech Drive
Mudd Room 3517
Evanston, IL 60208-3109

847-491-2970Email Nikos Hardavellas

Website

Nikos Hardavellas' Homepage

Parallel Architecture Group at Northwestern (PARAG@N)

Departments

Computer Science

Electrical and Computer Engineering

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Education

Ph.D. Computer Science, Carnegie Mellon University, Pittsburgh, PA

M.S. Computer Science, Carnegie Mellon University, Pittsburgh, PA

M.S. Computer Science, University of Rochester, Rochester, NY

B.S. Computer Science, University of Crete, Heraklion, Crete, Greece


Research Interests

Prof. Hardavellas works on parallel systems and computer architecture, primarily on techniques to enable extreme-scale multicore processors, novel memory systems, and practical quantum systems. His research aims to pave the way to energy-efficient computing by investigating ideas to combat dark silicon, and to speed up the execution of programs by several factors through parallelism extraction, novel architectures, blending of compilers, runtimes, operating systems and hardware, and the use of emerging technologies. Prof. Hardavellas' current work focuses on quantum chiplets, quantum dynamic decoupling, programmable memory systems, hybrid memory consistency models, and open hardware.


Selected Publications

  • Vijay Kandiah, Daniel Lustig, Oreste Villa, David Nellans and Nikos Hardavellas. Parsimony: Enabling SIMD/Vector Programming in Standard Compiler Flows. In Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization (CGO), Montreal, Canada, February 2023.
  • Brian Suchy, Souradip Ghosh, Aaron Nelson, Zhen Huang, Drew Kersnar, Siyuan Chai, Michael Cuevas, Alex Bernat, Gaurav Chaudhary, Nikos Hardavellas, Simone Campanoni, and Peter Dinda. CARAT CAKE: Replacing Paging via Compiler/Kernel Cooperation. In Proceedings of the 2022 Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Lausanne, Switzerland, March 2022.
  • T. Tomesh, P. Gokhale, V. Omole, G. Ravi, K. Smith, J. Viszlai, X. Wu, N. Hardavellas, M. Martonosi, F. Chong. SupermarQ: A Scalable Quantum Benchmark Suite. In Proceedings of the 28th IEEE International Symposium on High-Performance Computer Architecture (HPCA), Seoul, South Korea, February 2022. Best Paper Award. IEEE Micro Top Picks Honorable Mention.
  • V. Kandiah, S. Peverelle, M. Khairy, J. Pan, A. Manjunath, T. G. Rogers, T. M. Aamodt and N. Hardavellas. AccelWattch: A Power Modeling Framework for Modern GPUs. In Proceedings of the 54th IEEE/ACM International Symposium on Microarchitecture (MICRO), Athens, Greece, October 2021.
  • H. Han, T. Alexoudi, C. Vagionas, N. Pleros and N. Hardavellas. Pho$: A Case for Shared Optical Cache Hierarchies. In Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), July 2021. Best Paper Award Nomination.
  • B. Suchy, S. Campanoni, N. Hardavellas and P. Dinda. CARAT: A Case for Virtual Memory through Compiler- and Runtime-based Address Translation. In Proceedings of the 41st ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), London, UK, June 2020.
  • Y. Demir and N. Hardavellas. Energy Proportional Photonic Flattened-Butterfly Networks. In Proceedings of the 22nd IEEE International Symposium on High Performance Computer Architecture (HPCA), Barcelona, Spain, March 2016.
  • Y. Demir and N. Hardavellas. EcoLaser: An Adaptive Laser Control for Energy-Efficient On-Chip Photonic Interconnects. In Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), La Jolla, CA, August 2014.
  • Y. Demir, Y. Pan, S. Song, N. Hardavellas, G. Memik and J. Kim. Galaxy: A High-Performance Energy-Efficient Multi-Chip Architecture Using Photonic Interconnects. In Proceedings of the ACM International Conference on Supercomputing (ICS), pp. 303--312, Munich, Germany, June 2014.
  • N. Hardavellas, M. Ferdman, B. Falsafi and A. Ailamaki. Near-Optimal Cache Block Placement with Reactive Nonuniform Cache Architectures. IEEE Micro, Vol. 30(1), pp. 20-28, January/February 2010. IEEE Micro Top Picks from Computer Architecture Conferences.
  • R. Johnson, I. Pandis, N. Hardavellas, A. Ailamaki, and B. Falsafi. Shore-MT: A Scalable Storage Manager for the Multicore Era. In Proceedings of the 12th International Conference on Extending Database Technology (EDBT), pp. 24–35, Saint-Petersburg, Russia, March 2009. Test of Time Award.
  • T. F. Wenisch, S. Somogyi, N. Hardavellas, J. Kim, A. Ailamaki, and B. Falsafi. Temporal Streaming of Shared Memory. In Proceedings of the 32nd ACM/IEEE Annual International Symposium on Computer Architecture (ISCA), pp. 222–233, Madison, WI, June 2005.
  • R. J. Stets, S. Dwarkadas, N. Hardavellas, G. C. Hunt, L. Kontothanassis, S. Parthasarathy, and M. L. Scott. Cashmere-2L: Software Coherent Shared Memory on a Clustered Remote-Write Network. In Proceedings of the 16th ACM Symposium on Operating Systems Principles (SOSP), pp. 170–183, Saint Malo, France, October 1997.
  • L. Kontothanassis, G. C. Hunt, R. J. Stets, N. Hardavellas, M. Cierniak, S. Parthasarathy, W. Meira Jr., S. Dwarkadas, and M. L. Scott. VM-Based Shared Memory on Low-Latency, Remote-Memory-Access Networks. In Proceedings of the 24th ACM/IEEE Annual International Symposium on Computer Architecture (ISCA), pp. 157–169, Denver, CO, June 1997.